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preliminary datasheet analog front-end chip for multi-cells li+ battery pack AP9107 nov. 2012 rev 1. 1 bcd semiconductor manufacturing limited 1 general description AP9107 is an analog fron t-end chip especially for multi-cells li-ion/polymer battery pack application. it includes 8-channels analog switch, builds in passive balancing circuit for 6 channels with 65 discharge resistor, and linear regulator with 5ma capability which can offer low noise voltage reference for post adc circuit. AP9107 has four logic selection inputs (a/b/c/d). when all logic pins are set low, no channel is selected and the chip is turned off with shutdown mode. the a, b, c and d selection pins are compatible with ttl/cmos logic level, can be connected to mcu i/o port di rectly to select the right channel respectively. the vo ut is analog output pin to indicate exactly the voltage of each channel. aux7, aux8 pins are auxiliary channels, which can be connected to the ntc and/or ptc resistor to measure the battery pack temperature. AP9107 has 4 logic output pins as alo, blo, clo and dlo, which can transfer control logic for the upper chip if used in dual or triple chips in serial. AP9107 is available in standard package of tssop-24 (edp). features ? 6mv cell voltage matching error between e any 2 chs after software correlation ? integrated internal balancing circuit with 65 e discharge resistor ? built-in v ref , 5.0v/5.0ma with 1% ? e built-in logic transfer with level shift for e application with 2 or 3 chips in serial ? ultra low current in shutdown mode, 4.5 a ? up to 6-cells in serial battery pack application e with single chip ? up to 11-cells in serial battery pack application e with dual chips ? up to 16-cells in serial battery pack application e with triple chips ? compatible with ttl/cmos logic level applications ? e-bike battery pack ? e-moto battery pack figure 1. package type of AP9107 tssop-24 (edp)
preliminary datasheet analog front-end chip for multi-cells li+ battery pack AP9107 nov. 2012 rev 1. 1 bcd semiconductor manufacturing limited 2 pin configuration g package (tssop-24 (edp)) 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 11 12 14 13 vl vdd b6 b5 b4 b3 b2 b1 b0/gnd aux7 aux8 vref vout d c b a bal nc balo alo blo clo dlo figure 2. pin configurat ion of AP9107 (top view)
preliminary datasheet analog front-end chip for multi-cells li+ battery pack AP9107 nov. 2012 rev 1. 1 bcd semiconductor manufacturing limited 3 pin descriptions (note 1) pin number pin name function 1 vl level shift logic power supply 2 vdd power supply 3 b6 positive node of sixth battery cell 4 b5 positive node of fifth battery cell & negative node of sixth battery cell 5 b4 positive node of fourth battery cell & negative node of fifth battery cell 6 b3 positive node of third battery cell & negative node of fourth battery cell 7 b2 positive node of second battery cell & negative node of third battery cell 8 b1 positive node of first battery cell & negative node of second battery cell 9 b0(gnd) ground and negative node of first battery cell 10 aux7 auxiliary channel 7 11 aux8 auxiliary channel 8 12 vref reference voltage output 5v/5 ma with 1%, connect 1.0 f capacitor at least to gnd 13 vout cell voltage output pin 14 d channel selection logic input d 15 c channel selection logic input c 16 b channel selection logic input b 17 a channel selection logic input a 18 bal balance selection logic i nput, active high. set bal high, the chip is in balance mode; in this mode, v out is forced to 0v. set bal low, the chip is in normal mode; v out indicates channel input voltage respectively based on channel selection 19 nc no connected 20 balo balance selection logic output 21 alo channel selection logic output a 22 blo channel selection logic output b 23 clo channel selection logic output c 24 dlo channel selection logic output d note 1: vdd pin should always be connected to the positive node of top battery; voltage of vl pin should be equal to or larger than that of the vdd pin, and should not exceed v dd +5.0v.
preliminary datasheet analog front-end chip for multi-cells li+ battery pack AP9107 nov. 2012 rev 1. 1 bcd semiconductor manufacturing limited 4 truth table and relationship between input logic, output logic and active channel (note 2) v dd =21.6v, v l =v dd +4.4v=26v. logic input logic output balance status active channel output voltage (v out ) bal a b c d balo alo blo clo dlo 0 0 0 0 0 0 0 0 0 0 close (shutdown mode) n/a 0v (shutdown mode) 0 0 0 0 1 0 0 1 1 1 close qd1 b1 vs. b0 0 0 0 1 0 0 0 1 1 1 close qd2 b2 vs. b1 0 0 0 1 1 0 0 1 1 1 close qd3 b3 vs. b2 0 0 1 0 0 0 0 1 1 1 close qd4 b4 vs. b3 0 0 1 0 1 0 0 1 1 1 close qd5 b5 vs. b4 0 0 1 1 0 0 0 1 1 1 close qd7 4*(aux7 vs. gnd) 0 0 1 1 1 0 0 1 1 1 close qd8 4*(aux8 vs. gnd) 0 1 0 0 0 0 1 0 0 0 close qd6 b6 vs. b5 0 1 0 0 1 0 0 0 0 1 close qd6 b6 vs. b5 0 1 0 1 0 0 0 0 1 0 close qd6 b6 vs. b5 0 1 0 1 1 0 0 0 1 1 close qd6 b6 vs. b5 0 1 1 0 0 0 0 1 0 0 close qd6 b6 vs. b5 0 1 1 0 1 0 0 1 0 1 close qd6 b6 vs. b5 0 1 1 1 0 0 0 1 1 0 close qd6 b6 vs. b5 0 1 1 1 1 0 0 1 1 1 close qd6 b6 vs. b5 1 0 0 0 0 1 0 0 0 0 n/a n/a 0v 1 0 0 0 1 1 0 1 1 1 b1 vs. b0 qd1 0v 1 0 0 1 0 1 0 1 1 1 b2 vs. b1 qd2 0v 1 0 0 1 1 1 0 1 1 1 b3 vs. b2 qd3 0v 1 0 1 0 0 1 0 1 1 1 b4 vs. b3 qd4 0v 1 0 1 0 1 1 0 1 1 1 b5 vs. b4 qd5 0v 1 0 1 1 0 1 0 1 1 1 n/a n/a 0v 1 0 1 1 1 1 0 1 1 1 n/a n/a 0v 1 1 0 0 0 1 1 0 0 0 b6 vs. b5 qd6 0v 1 1 0 0 1 1 0 0 0 1 b6 vs. b5 qd6 0v 1 1 0 1 0 1 0 0 1 0 b6 vs. b5 qd6 0v 1 1 0 1 1 1 0 0 1 1 b6 vs. b5 qd6 0v 1 1 1 0 0 1 0 1 0 0 b6 vs. b5 qd6 0v 1 1 1 0 1 1 0 1 0 1 b6 vs. b5 qd6 0v 1 1 1 1 0 1 0 1 1 0 b6 vs. b5 qd6 0v 1 1 1 1 1 1 0 1 1 1 b6 vs. b5 qd6 0v
preliminary datasheet analog front-end chip for multi-cells li+ battery pack AP9107 nov. 2012 rev 1. 1 bcd semiconductor manufacturing limited 5 channel balance chart (note 2) note 2: in balance mode, output voltage (vout pin) is forced to 0v, and it does not indicate the channel input voltage. balance current between selected channels is activ e until bal is set low. once bal is set low, v out will indicate selected channel input voltage correctly. make sure the set up time of channel selection is 1.0ms at least. balance current is generated after ?t? period, 500 s in typical.
preliminary datasheet analog front-end chip for multi-cells li+ battery pack AP9107 nov. 2012 rev 1. 1 bcd semiconductor manufacturing limited 6 functional block diagram figure 3. functional block diagram of AP9107
preliminary datasheet analog front-end chip for multi-cells li+ battery pack AP9107 nov. 2012 rev 1. 1 bcd semiconductor manufacturing limited 7 ordering information AP9107 - circuit type g1: green package g: tssop-24 (edp) tr: tape & reel package temperature range part number marking id packing type tssop-24 (edp) (note 3) -40 to 85 c AP9107gtr-g1 AP9107g-g1 tape & reel bcd semiconductor's pb-free products, as designated with "g1" suffix in the part number, are rohs compliant and green. note 3: for the thermal pad size, please see the option 2 of mechanical dimensions in page 16.
preliminary datasheet analog front-end chip for multi-cells li+ battery pack AP9107 nov. 2012 rev 1. 1 bcd semiconductor manufacturing limited 8 absolute maximum ratings (note 4) parameter symbol value unit supply voltage v dd -0.3 to 36 v logic voltage vl to vdd -0.3 to 5 v vl to gnd -0.3 to 36 v voltage between b n and b n+1 v cell -0.3 to 5 v voltage between aux7/aux8 and gnd v aux -0.3 to 1.25 v operating junction temperature range t j 150 oc storage temperature range t stg -65 to 150 oc lead temperature (soldering, 10sec) t lead 260 oc thermal resistance (note 5) ja 40 oc / w esd (machine model) 200 v esd (human body model) 2000 v note 4: stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, and functional op eration of the device at these or any other conditions beyond those indicated under ?recommended operating co nditions? is not implied. exposure to ?absolute maximum ratings? for extended periods may affect device reliability. note 5: chip is soldered to copper (1oz, 100mm 2 ) with 10*phi 0.5mm vias. recommended operating conditions parameter symbol min max unit supply voltage v dd 6.0 27 v battery cell voltage v cell 2.0 4.5 v input voltage (b6 vs. b5, b5 vs. b4, b4 vs. b3, b3 vs. b2, b2 vs. b1, b1 vs. gnd) v in 2.0 4.5 v aux7/8 vs. gnd 0.5 1.125 operating ambient temperature t a -40 85 c input logic level v il /v ih 0 5.0 v
preliminary datasheet analog front-end chip for multi-cells li+ battery pack AP9107 nov. 2012 rev 1. 1 bcd semiconductor manufacturing limited 9 electrical characteristics v dd =21.6v, v l =v dd +4.4v=26v, t a =25c, bold typeface applies over full temperature -40c t a 85c ranges, unless otherwise specified. parameter symbol test conditions min typ max unit supply voltage v dd 6.0 27 v quiescent current i q 0.28 0.4 m logic current i l 8.0 ? shutdown current i shut set a, b, c, d and bal low 4.5 8.0 ? vref output voltage v ref 4.95 5.0 5.05 v vref output current i ref 3 5 ma balance discharge resistor r bal 65 switch bias current i bias for b1, b2, b3, b4, b5 and b6 pin 25 40 ? for aux7, aux8 pin 1.0 channel matching error between any 2 channels after correlations e match set all channels dc: 2.5v to 4.2v, (v max -v min )/average(ch1 to ch8) -6 6 mv gain (note 6) gain ch1, ch2, ch3, ch4, ch5, ch6 1.0 v/v ch7, ch8 0.25 channel switching and set-up time t set 1.0 ms logic input (voltage mode) logic input high level v ih a, b, c, d, bal 1.2 5.0 v logic input low level v il a, b, c, d, bal 0 0.5 v input leakage current i leak set a, b, c, d bal 0v -1.0 1.0 a pull down current i pull-down set a, b, c, d bal 5.0v 1.0 a logic output (voltage mode) logic input low level v ol alo, blo, clo, dlo, balo v dd v logic input high level v oh alo, blo, clo, dlo, balo v l v note 6: ch1-b1 vs. b0; ch2-b2 vs. b1; ch3-b3 vs. b2; ch4-b4 vs. b3; ch5-b5 vs. b4; ch6-b6 vs. b5; ch7-aux7 vs. b0; ch8-aux8 vs. b0.
preliminary datasheet analog front-end chip for multi-cells li+ battery pack AP9107 nov. 2012 rev 1. 1 bcd semiconductor manufacturing limited 10 typical application AP9107 can be used for multi-cells (3 to 6-cells in serial) battery pack application. below is the recommended typical application circuit for 6 cells in series. vl 1 vdd 2 dlo 24 aux7 10 b0/gnd 9 b1 8 b2 7 b3 6 b4 5 b5 4 b6 3 b 16 a 17 bal 18 vout 13 nc 19 balo 20 alo 21 blo 22 clo 23 cell1 cell2 cell3 cell4 cell5 cell6 mcu bal 1 a 2 b 3 c 4 adc 6 vcc 7 gnd 8 5.1 5.1 5.1 5.1 5.1 5.1 50 1% r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 rt1 330k 100k 42k 1m c1 0.1 f/10v c2 0.1 f/10v c3 0.1 f/10v c4 0.1 f/10v c5 0.1 f/10v c6 c7 10 f/50v c8 c9 to AP9107 u1 u2 vref vcell-t +5.0v vcell-t vref aux8 11 vref 12 c 15 d 14 d 5 c10 0.1 f/10v 0.1 f/10v 1 f/10v 0.1 f/10v 50 1% figure 4. 6-cells battery (single chip) application for AP9107
preliminary datasheet analog front-end chip for multi-cells li+ battery pack AP9107 nov. 2012 rev 1. 1 bcd semiconductor manufacturing limited 11 truth table for 6-cells (si ngle chip) battery application logic input balance status output voltage bal a b c d 0 0 0 0 0 close (shutdown mode) 0v (shutdown mode) 0 0 0 0 1 close vcell1 0 0 0 1 0 close vcell2 0 0 0 1 1 close vcell3 0 0 1 0 0 close vcell4 0 0 1 0 1 close vcell5 0 0 1 1 0 close 4*(aux7) 0 0 1 1 1 close 4*(aux8) 0 1 0 0 0 close vcell6 0 1 0 0 1 close vcell6 0 1 0 1 0 close vcell6 0 1 0 1 1 close vcell6 0 1 1 0 0 close vcell6 0 1 1 0 1 close vcell6 0 1 1 1 0 close vcell6 0 1 1 1 1 close vcell6 1 0 0 0 0 n/a 0v 1 0 0 0 1 vcell1 0v 1 0 0 1 0 vcell2 0v 1 0 0 1 1 vcell3 0v 1 0 1 0 0 vcell4 0v 1 0 1 0 1 vcell5 0v 1 0 1 1 0 n/a 0v 1 0 1 1 1 n/a 0v 1 1 0 0 0 vcell6 0v 1 1 0 0 1 vcell6 0v 1 1 0 1 0 vcell6 0v 1 1 0 1 1 vcell6 0v 1 1 1 0 0 vcell6 0v 1 1 1 0 1 vcell6 0v 1 1 1 1 0 vcell6 0v 1 1 1 1 1 vcell6 0v
preliminary datasheet analog front-end chip for multi-cells li+ battery pack AP9107 nov. 2012 rev 1. 1 bcd semiconductor manufacturing limited 12 typical application (continued) AP9107 can be used for up to 11-cells in serial battery pack application with dual chips. below is the recommended typical application circuit fo r 11 cells in series battery pack. vl 1 vdd 2 dlo 24 aux7 10 b0/gnd 9 b1 8 b2 7 b3 6 b4 5 b5 4 b6 3 b 16 a 17 bal 18 vout 13 nc 19 balo 20 alo 21 blo 22 clo 23 cell1 cell2 cell3 cell4 cell5 mcu bal 1 a 2 b 3 c 4 adc 6 vcc 7 gnd 8 5.1 5.1 5.1 5.1 5.1 5.1 r1 r2 r3 r4 r5 r6 r7 r9 r10 r11 rt1 330k 100k 20k 1m c1 0.1 f/10v c2 0.1 f/10v c3 0.1 f/10v c4 0.1 f/10v c5 0.1 f/10v c7 0.1 f/10v c8 c9 to AP9107(lower) u1 u3 vref vcell-t +5.0v vref aux8 11 vref 12 c 15 d 14 d 5 vl 1 vdd 2 dlo 24 aux7 10 b0/gnd 9 b1 8 b2 7 b3 6 b4 5 b5 4 b6 3 b 16 a 17 bal 18 vout 13 nc 19 balo 20 alo 21 blo 22 clo 23 cell6 cell7 cell8 cell9 cell10 cell11 5.1 5.1 5.1 5.1 5.1 5.1 50 1% r12 r13 r14 r15 r16 r17 r18 r19 r20 rt1 330k 100k c10 0.1 f/10v c11 0.1 f/10v c12 0.1 f/10v c13 0.1 f/10v c14 0.1 f/10v c15 0.1 f/10v c17 to AP9107(upper) u2 vref1 vcell-t vref1 aux8 11 vref 12 c 15 d 14 r8 0.1 f/10v 0.1 f/10v 0.1 f/10v 1 f/10v 1 f/10v 50 1% 50 1% 50 1% c16 10 f/63v c6 0.1 f/10v c18 c19 figure 5. 11-cells battery (dual chips) application for AP9107
preliminary datasheet analog front-end chip for multi-cells li+ battery pack AP9107 nov. 2012 rev 1. 1 bcd semiconductor manufacturing limited 13 truth table for 11-cells (dual chips) battery application logic input (lower) logic input (upper) balance status output voltage bal a b c d bal a b c d 0 0 0 0 0 0 0 0 0 0 close (shutdown mode) 0v (shutdown mode) 0 0 0 0 1 0 0 1 1 1 close vcell1 0 0 0 1 0 0 0 1 1 1 close vcell2 0 0 0 1 1 0 0 1 1 1 close vcell3 0 0 1 0 0 0 0 1 1 1 close vcell4 0 0 1 0 1 0 0 1 1 1 close vcell5 0 0 1 1 0 0 0 1 1 1 close 4*(aux7)(lower) 0 0 1 1 1 0 0 1 1 1 close 4*(aux8) (lower) 0 1 0 0 0 0 1 0 0 0 close vcell11 0 1 0 0 1 0 0 0 0 1 close vcell6 0 1 0 1 0 0 0 0 1 0 close vcell7 0 1 0 1 1 0 0 0 1 1 close vcell8 0 1 1 0 0 0 0 1 0 0 close vcell9 0 1 1 0 1 0 0 1 0 1 close vcell10 0 1 1 1 0 0 0 1 1 0 close 4*(aux7)(upper) 0 1 1 1 1 0 0 1 1 1 close 4*(aux8)(upper) 1 0 0 0 0 1 0 0 0 0 n/a 0v 1 0 0 0 1 1 0 1 1 1 vcell1 0v 1 0 0 1 0 1 0 1 1 1 vcell2 0v 1 0 0 1 1 1 0 1 1 1 vcell3 0v 1 0 1 0 0 1 0 1 1 1 vcell4 0v 1 0 1 0 1 1 0 1 1 1 vcell5 0v 1 0 1 1 0 1 0 1 1 1 n/a 0v 1 0 1 1 1 1 0 1 1 1 n/a 0v 1 1 0 0 0 1 1 0 0 0 vcell11 0v 1 1 0 0 1 1 0 0 0 1 vcell6 0v 1 1 0 1 0 1 0 0 1 0 vcell7 0v 1 1 0 1 1 1 0 0 1 1 vcell8 0v 1 1 1 0 0 1 0 1 0 0 vcell9 0v 1 1 1 0 1 1 0 1 0 1 vcell10 0v 1 1 1 1 0 1 0 1 1 0 n/a 0v 1 1 1 1 1 1 0 1 1 1 n/a 0v
preliminary datasheet analog front-end chip for multi-cells li+ battery pack AP9107 nov. 2012 rev 1. 1 bcd semiconductor manufacturing limited 14 typical application (continued) AP9107 can be used for up to 16-cells in serial battery pack application with triple chips. below is the recommended typical application circuit fo r 16 cells in series battery pack. figure 6. 16-cells battery (triple chips) application for AP9107
preliminary datasheet analog front-end chip for multi-cells li+ battery pack AP9107 nov. 2012 rev 1. 1 bcd semiconductor manufacturing limited 15 truth table for 16-cells (triple chips) battery application logic input(lower) logic input (middle) logic input (upper) balance status output voltage bal a b c d bal a b c d bal a b c d 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 close (shutdown mode) 0v (shutdown mode) 0 0 0 0 1 0 0 1 1 1 0 0 1 1 1 close vcell1 0 0 0 1 0 0 0 1 1 1 0 0 1 1 1 close vcell2 0 0 0 1 1 0 0 1 1 1 0 0 1 1 1 close vcell3 0 0 1 0 0 0 0 1 1 1 0 0 1 1 1 close vcell4 0 0 1 0 1 0 0 1 1 1 0 0 1 1 1 close vcell5 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 close 4*(aux7)(lower) 0 0 1 1 1 0 0 1 1 1 0 0 1 1 1 close 4*(aux8)(lower) 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 close vcell16 0 1 0 0 1 0 0 0 0 1 0 0 1 1 1 close vcell6 0 1 0 1 0 0 0 0 1 0 0 0 1 1 1 close vcell7 0 1 0 1 1 0 0 0 1 1 0 0 1 1 1 close vcell8 0 1 1 0 0 0 0 1 0 0 0 0 1 1 1 close vcell9 0 1 1 0 1 0 0 1 0 1 0 0 1 1 1 close vcell10 0 1 1 1 0 0 0 1 1 0 0 0 1 1 1 close 4*(aux7)(middle) 0 1 1 1 1 0 0 1 1 1 0 0 1 1 1 close 4*(aux8)(middle) 0 1 0 0 1 0 1 0 0 1 0 0 0 0 1 close vcell11 0 1 0 1 0 0 1 0 1 0 0 0 0 1 0 close vcell12 0 1 0 1 1 0 1 0 1 1 0 0 0 1 1 close vcell13 0 1 1 0 0 0 1 1 0 0 0 0 1 0 0 close vcell14 0 1 1 0 1 0 1 1 0 1 0 0 1 0 1 close vcell15 0 1 1 1 0 0 1 1 1 0 0 0 1 1 0 close 4*(aux7)(upper) 0 1 1 1 1 0 1 1 1 0 0 0 1 1 1 close 4*(aux8)(upper) 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 n/a 0v 1 0 0 0 1 0 0 1 1 1 0 0 1 1 1 vcell1 0v 1 0 0 1 0 0 0 1 1 1 0 0 1 1 1 vcell2 0v 1 0 0 1 1 0 0 1 1 1 0 0 1 1 1 vcell3 0v 1 0 1 0 0 0 0 1 1 1 0 0 1 1 1 vcell4 0v 1 0 1 0 1 0 0 1 1 1 0 0 1 1 1 vcell5 0v 1 0 1 1 0 0 0 1 1 1 0 0 1 1 1 n/a 0v 1 0 1 1 1 0 0 1 1 1 0 0 1 1 1 n/a 0v 1 1 0 0 0 0 1 0 0 0 0 1 0 0 0 vcell16 0v 1 1 0 0 1 0 0 0 0 1 0 0 1 1 1 vcell6 0v 1 1 0 1 0 0 0 0 1 0 0 0 1 1 1 vcell7 0v 1 1 0 1 1 0 0 0 1 1 0 0 1 1 1 vcell8 0v 1 1 1 0 0 0 0 1 0 0 0 0 1 1 1 vcell9 0v 1 1 1 0 1 0 0 1 0 1 0 0 1 1 1 vcell10 0v 1 1 1 1 0 0 0 1 1 0 0 0 1 1 1 n/a 0v 1 1 1 1 1 0 0 1 1 1 0 0 1 1 1 n/a 0v 1 1 0 0 1 0 1 0 0 1 0 0 0 0 1 vcell11 0v 1 1 0 1 0 0 1 0 1 0 0 0 0 1 0 vcell12 0v 1 1 0 1 1 0 1 0 1 1 0 0 0 1 1 vcell13 0v 1 1 1 0 0 0 1 1 0 0 0 0 1 0 0 vcell14 0v 1 1 1 0 1 0 1 1 0 1 0 0 1 0 1 vcell15 0v 1 1 1 1 0 0 1 1 1 0 0 0 1 1 0 n/a 0v 1 1 1 1 1 0 1 1 1 0 0 0 1 1 1 n/a 0v
preliminary datasheet analog front-end chip for multi-cells li+ battery pack AP9107 nov. 2012 rev 1. 1 bcd semiconductor manufacturing limited 16 mechanical dimensions tssop-24 (edp) unit: mm(inch) gage plane 0.250(0.010) seating plane 0.500(0.020) 0.700(0.028) 1.000(0.039) 0 8 0.650(0.026) 0.190(0.007) 0.300(0.012) d 4.300(0.169) 4.500(0.177) 6.200(0.244) 6.600(0.260) e 1.200(0.047)max 0.000(0.000) 0.150(0.006) 112 13 24 note: eject hole, oriented hole and mold mark is optional. . 7.700(0.303) 7.900(0.311) 0.200(0.008) 0.080(0.003) symbol d e min(mm) max(mm) max(mm) min(mm) min(inch) min(inch) max(inch) max(inch) option1 option2 1.500 2.700 1.800 3.000 3.900 2.700 3.000 4.200 0.059 0.071 0.106 0.118 0.106 0.118 0.154 0.165
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wafer fab shanghai sim-bcd semiconductor manufacturing limited 800, yi shan road, shanghai 200233, china tel: +86-21-6485 1491, fax: +86-21-5450 0008 bcd semiconductor manufacturing limited main site regional sales office shenzhen office shanghai sim-bcd semiconductor manuf acturing co., ltd. shenzhen office advanced analog circuits (shanghai) corporation shenzhen office room e, 5f, noble center, no.1006, 3rd fuzhong road, futian district, shenzhen 518026, china tel: +86-755-8826 7951 fax: +86-755-8826 7865 taiwan office bcd semiconductor (taiwan) company limited 4f, 298-1, rui guang road, nei-hu district, taipei, taiwan tel: +886-2-2656 2808 fax: +886-2-2656 2806 usa office bcd semiconductor corporation 30920 huntwood ave. hayward, ca 94544, u.s.a tel : +1-510-324-2988 fax: +1-510-324-2788 - ic design group advanced analog circuits (shanghai) corporation 8f, zone b, 900, yi shan road, shanghai 200233, china tel: +86-21-6495 9539, fax: +86-21-6485 9673 bcd semiconductor manufacturing limited http://www.bcdsemi.com bcd semiconductor manufacturing limited important notice bcd semiconductor manufacturing limited reserves the right to make changes without further not ice to any products or specifi- cations herein. bcd semiconductor manufacturing limited does not as sume any responsibility for us e of any its products for any particular purpose, nor does bcd semiconductor manufacturi ng limited assume any liability aris ing out of the application or use of any its products or circui ts. bcd semiconductor manufacturing limited does not convey any license under its patent rights or other rights nor the rights of others. - wafer fab shanghai sim-bcd semiconductor manufacturing co., ltd. 800 yi shan road, shanghai 200233, china tel: +86-21-6485 1491, fax: +86-21-5450 0008 main site regional sales office shenzhen office shanghai sim-bcd semiconductor manuf acturing co., ltd., shenzhen office unit a room 1203, skyworth bldg., gaoxin ave.1.s., nanshan district, shenzhen, china tel: +86-755-8826 7951 fax: +86-755-8826 7865 taiwan office bcd semiconductor (taiwan) company limited 4f, 298-1, rui guang road, nei-hu district, taipei, taiwan tel: +886-2-2656 2808 fax: +886-2-2656 2806 usa office bcd semiconductor corp. 30920 huntwood ave. hayward, ca 94544, usa tel : +1-510-324-2988 fax: +1-510-324-2788 - headquarters bcd semiconductor manufacturing limited no. 1600, zi xing road, shanghai zizhu sc ience-based industrial park, 200241, china tel: +86-21-24162266, fax: +86-21-24162277 important notice bcd semiconductor manufacturing limited reserves the right to make changes without further not ice to any products or specifi- cations herein. bcd semiconductor manufacturing limited does not as sume any responsibility for us e of any its products for any particular purpose, nor does bcd semiconductor manufacturi ng limited assume any liability aris ing out of the application or use of any its products or circui ts. bcd semiconductor manufacturing limited does not convey any license under its patent rights or other rights nor the rights of others. - wafer fab shanghai sim-bcd semiconductor manufacturing limited 800, yi shan road, shanghai 200233, china tel: +86-21-6485 1491, fax: +86-21-5450 0008 bcd semiconductor manufacturing limited main site regional sales office shenzhen office shanghai sim-bcd semiconductor manuf acturing co., ltd. shenzhen office advanced analog circuits (shanghai) corporation shenzhen office room e, 5f, noble center, no.1006, 3rd fuzhong road, futian district, shenzhen 518026, china tel: +86-755-8826 7951 fax: +86-755-8826 7865 taiwan office bcd semiconductor (taiwan) company limited 4f, 298-1, rui guang road, nei-hu district, taipei, taiwan tel: +886-2-2656 2808 fax: +886-2-2656 2806 usa office bcd semiconductor corporation 30920 huntwood ave. hayward, ca 94544, u.s.a tel : +1-510-324-2988 fax: +1-510-324-2788 - ic design group advanced analog circuits (shanghai) corporation 8f, zone b, 900, yi shan road, shanghai 200233, china tel: +86-21-6495 9539, fax: +86-21-6485 9673 bcd semiconductor manufacturing limited http://www.bcdsemi.com bcd semiconductor manufacturing limited

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